This invention relates generally to integrated circuit memories, and more particularly, to read-only integrated circuit memories (ROMS).
As is known in the art, one type of digital memory is a read-only memory (ROM). One type of such ROM is a so-called X-ROM described in an article entitled "A 100ns 150 mW 64K Bit ROM" by D. R. Wilson and P. R. Schroeder, ISSCC DIGEST OF TECHNICAL PAPERS, pp. 152-153, 273, Feb. 1978. This paper discloses a memory having a first set of horizontally extending row electrical conductors or row lines, and two sets of vertically extending electrical conductors, one set called data lines and the other set called column lines. The data lines and column lines are physically arranged in an alternating pattern. The column lines are themselves alternately interconnected to form two groups of column lines. The bit lines carry data from the memory cells to sense amplifiers. Memory cells are arranged in an array NxM in regions bounded by the two sets of column lines and the set of row lines. Each memory cell is coupled to an adjacent column line, an adjacent bit line, and an adjacent row line. Memory cells are selected by enabling one column line and one row line. Therefore, each row address conductor has M memory cells coupled thereto and each column line has 2N memory cells coupled thereto. During an access of the memory, one of the row lines is enabled and one of the two groups of column lines is enabled. This causes those memory cells coupled to the enabled row line and to the enabled column lines to transfer their stored information to their respective bit lines. Each column line is heavily loaded capacitively because of the 2N memory cells coupling to it. This capacitive loading reduces access time of the memory due to a delay necessary to insure complete charging of the heavily loaded column lines. To reduce this delay, large, high power column line drivers are required. Therefore, with each access of the memory, one set of the column line and associated drivers are active, causing high power dissipation and high electrical noise generation. Due to the physical structure of the memory, these column line drivers and associated column line decoders are located apart from row line drivers and associated row line decoders. By using separate row line and column line decoders with large column line drivers, less area is available to the memory for memory cells.
It is therefore an object of this invention to provide a high density memory with a structure that has reduced loading on the column lines to allow smaller, lower power drivers for the column lines.
It is a further object of this invention to provide a high density memory with a structure that allows a common decoder circuitry for both column and row lines.
Another object of this invention is to provide a decoder which uses common circuitry to drive the column and row drivers.